Aldec, Inc., a industry-leading Electronic Design Automation (EDA) company delivering innovative design creation, simulation and verification solutions to assist in the development of complex FPGA, ASIC, SoC and embedded system designs, announces the latest release of its mixed-language, advanced verification platform, Riviera-PRO 2014.06. This release extends Riviera-PRO’s already powerful visual mapping capabilities for UVM verification environments. Aldec introduces UVM Toolbox to interpret complex UVM verification environments into an easily readable, hierarchical format. With best-in-class SystemVerilog support and now more powerful UVM debugging environment, Riviera-PRO significantly increases the productivity of design and verification engineers.
UVM Toolbox displays object properties for components selected within the hierarchy, and is synchronized with UVM Graph, Class Viewer and HDL Editor features within Riviera-PRO to deliver a seamless debugging experience.
The 2014.06 release of Riviera-PRO also includes numerous new features, enhancements and performance optimizations. For additional information, tutorials, visit https://www.aldec.com/en/products/functional_verification/riviera-pro
About Aldec Inc.
Aldec, Inc. is an industry-leading Electronic Design Automation (EDA) company delivering innovative design creation, simulation and verification solutions to assist in the development of complex FPGA, ASIC, SoC and embedded system designs.
Aldec delivers high quality EDA solutions for government, military, aerospace, telecommunications, automotive and safety critical applications. Large companies including IBM, GE, Qualcomm, Rohde and Schwarz, Bosch, Texas Instruments, Applied Micro, Hewlett Packard, Toshiba, Intel, NEC, Mitsubishi, LG, Hitachi, NASA, Invensys, Westinghouse, Raytheon, Panasonic, Lockheed Martin, Samsung, as well as mid-size and small firms utilize Aldec EDA verification suites to boost product performance, cut design development cycles and reduce cost.
Name: Aldec Riviera-PRO
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